1. Field of the Invention
This invention relates to integrated circuit packaging, and more particularly to an efficiently designed integrated circuit flip-chip die providing access to chip signals.
2. Description of the Related Art
Modern high performance integrated circuit, or IC, chips require large numbers of interconnections between the upper level IC structure, or die, and the lower level IC structure, or package. The large number of interconnections are necessary to perform complex operations. Prior methods for providing these interconnections include wire bonding, wherein the die is mounted to the package or substrate with connections between the top surface of the die and the surface of the package. The die and package are then mounted to the motherboard. Another known method for providing connections is through tape automated bonding (TAB). These methods are inherently inefficient for providing power and I/O to the die because limited space is available on the periphery of the die for wire bond or tape pads. Space at the periphery of the die which must be used for bonding translates into space which is unavailable for active circuitry. Further, the resistance and limited inductance associated with the wiring connecting the surface of the die to the package is frequently inadequate for ICs having high performance requirements.
As modern ICs perform numerous functions, package terminals and die conductors are constantly requiring a greater number of I/O and power connections. With current ICs sometimes requiring thousands of connections within a limited space on the die, terminal sizing and spacing must be highly precise in order to form the proper connection between the die and the terminal pattern formed on the associated package.
A method used to join the die to the package which provides adequate bonding and power-I/O capability is the "flip-chip" packaging process. The flip-chip process utilizes an IC flip-chip , which is a monolithic semiconductor unit having bead-like solder bump terminals provided on one face of the chip. These bumps are densely packed together on the die surface, thereby facilitating electrical connections to the substrate. A flip-chip configuration provides access to more core area for a given die size. Bump pitches of 250 micrometers on the surface of the flip-chip is typical. Allowing bumps over active circuitry yields greater silicon utilization. The proximity of the solder bumps on the die to the associated terminals on the package have the further benefit of decreasing the overall resistance in transmitting power or signals between the package and the die, improving overall system performance.
The problem with flip-chip designs is providing an efficient arrangement and orientation of the interconnections from the bumps to the outlying packaging. High performance ICs frequently require hundreds or even thousands of interconnections for input/output (I/O) or power and ground. Flip-chip interconnections must satisfy power ratio constraints, where the number of I/O interconnections drive the total number of power connections on the chip. The ratio between the number of I/O connections and power connections to support modern chip specifications are in the 4 to 1 range. I/O to power ratios of 5 to 1 or 6 to 1 are not unusual. These power ratios translate into a requirement that no more than four times as many I/O connections as power source connections can exist between the die and the package.
Pitch requirements typically mandate regular intervals between the bumps, further limiting bump placement and organization. Current pitch requirements for typical package-die arrangements are approximately 8 to 10 mils (center-to-center) between bumps for a flip-chip configuration.
It is an object of the current invention to provide an adaptable and efficient flip-chip distribution on the surface of a die for a packaging arrangement requiring hundreds or thousands of interconnections between the semiconductor die and package, whereby the arrangement provides maximum usage of the die surface for a given pitch ratio.
It is a further object of the current invention to provide an adaptable packaging arrangement able to support and efficiently operate an IC chip with a signal to power ratio down to four to one and an I/O cell pitch of approximately 2.5 mils.
It is another object of the current invention to provide an adaptable packaging arrangement which adequately and efficiently provides power to the chip core while satisfying the aforementioned design constraints.